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Race Logic Synthesis at APCCAS-10




Terence Chan Presented Advanced Race Logic Synthesis Technologies at APCCAS-10

January 15, 2011

Terence Chan, CEO and President of Dynetix Design Solutions Inc, presented a paper on the state-of-the-art race logic synthesis technologies at the IEEE Asian Pacific Conference of Circuits and Systems 2010 (APCCAS-10), in Kuala Lumpur, Malaysia, on December 9, 2010.  The advanced race logic synthesis technologies are US and international patent pending. They can automatically re-synthesize race logic in large-scale, deep submicron SoC, ASIC, FPGA and custom IC designs, and render V2simTM produces consistent simulation results for those circuits, on advanced multi-CPUs/cores computers.  

According to Terence Chan, race logic has been the major obstacle for the wide-spread adoption of  V2simTM a state-of-the-art multi-CPU, 32/64-bit HDL/ESL simulator, as IC designs are reluctant and/or unable to fix race logic in their designs and third party IP cores. With the new race logic synthesis technologies,  IC designers can now use V2simTM and   RaceCheckTM as turnkey tools to drastically cut down their IC development time by 30% or more, improve functional coverage and time to market. regardless of their designs contain race logic or not.

 Both   V2simTM and RaceCheckTM products are now in production release.


For More Information Contact:

Dynetix Design Solutions
3268 Ridgefield Way, Dublin, CA 94568
Tel: 925-833-7851
Internet: info@dynetix.com





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