RaceCheck^TM Product Features

• State-of-the-art static and dynamic race logic analysis technologies for comprehensive and precise race logic detection
• Static race logic checker uses signals' timing and functional information to derive accurate audit results and to filter out false violations
• Dynamic race logic checker uses V2Sim^TM advanced multithreaded (US 6,466,898, CA 2,397,302) HDL simulation technologies to detect "real-life" race events
• Static and dynamic race logic analysis can be deployed separately or together, and used in all stages of IC's development
• Based on US patent US 7,334,203 and US 7,757,121 technologies
• Single kernel for seamless verification of VHDL, Verilog, SystemVerilog, PSL and SystemC designs
• 64-bit processing on industrial standard 64-bit platforms
• Complements V2Sim^TM and other EDA verification tools for true 100% functional coverage
• Supports deep submicron ASIC, FPGA, SoC and custom IC design methodologies

Key Benefits

• Reveals hard-to-detect race logic not covered by other EDA verification tools
• Significantly minimizes intermittent IC product failures in the field, and products recall
• Complements V2Sim^TM to aid users achieve 100% functional coverage of their regression test suites
• Ensures IC designs are "portable" across different verification tools, and can be verified by V2Sim^TM

• 64-bit kernel to handle any large-scale SoC designs with billions of logic gates 

• Designed for SoC: allows users mix-and-match IP's coded in any Verilog, VHDL, SystemVerilog , PSL and SystemC languages

Supported Platforms

• Any  single-/multi-core computers, running Linux, Windows or UNIX

Supported Languages

• IEEE 1364-2005 (Verilog)
• IEEE 1076 (VHDL-2008)
• IEEE 1164 (Vital)
• IEEE 1800 (SystemVerilog)
• IEEE 1666 (SystemC)
• IEEE 1850 (PSL)

Please email us for further product information

Copyright © Dynetix Design Solutions Inc.